1. Technical Field
The present invention relates to a driving device of a display device, and in particular, relates to a driving device of a display device that supplies voltage, that corresponds to display data, to a display device and drives the display device.
2. Related Art
A driving device, that is equipped with a source driver that drives data lines and a gate driver that drives gate lines, is connected to an active-matrix-type display device (e.g., a TFT (Thin Film Transistor)-LCD (Liquid Crystal Display), or the like) in which the plural data lines are provided along the X direction, the plural gate lines are provided along the Y direction, and display cells (pixels) are respectively provided at the positions of intersection between the individual data lines and the individual gate lines. Display data of one line, which is formed from pixels corresponding to a same gate line, is inputted to this type of display device in order from a data source such as a graphic processor or the like, at each cycle of a horizontal synchronizing signal.
At each cycle of the horizontal synchronizing signal, the source driver of the driving device transfers display data of one line, that has been successively inputted from the data source, to a shift register and holds the data in latches, and, by level shifters, decoder circuits and amplification circuits, generates data voltages corresponding to the display data of one line that was inputted in the previous cycle, and supplies the generated data voltages to the individual data lines and writes the data voltages to the respective pixels of one line. Further, the gate driver of the driving device supplies a gate signal to a single gate line, and, at each cycle of the horizontal synchronizing signal, switches the gate line to which the gate signal is supplied. Due thereto, the driving device is driven, and an image expressed by the display data is displayed on the display device.
In relation to the above, Japanese Patent Application Laid-Open (JP-A) No. 2001-166741 discloses a structure in which pre-charging circuits, that generate voltages, at which the levels of the gradation voltages corresponding to the display data are shifted, and supplies the generated voltages to the drain signal lines during a pre-charging period, are provided between decoder circuits and output amplification circuits of a drain driver.
Further, JP-A No. 2009-139538 discloses a technique of providing a second decoder, that selects pre-charge voltages corresponding to image data from plural pre-charge voltages and outputs the selected pre-charge voltages, and supplying, to data lines, the pre-charge voltages outputted from the second decoder.
As the operating speeds of display devices are made to be faster, an increase in operating speed is demanded as well of driving devices that drive display devices. At the source driver of the above-described driving device, conventionally, as shown as an example in FIG. 6A, the operating speed of the amplification circuit, that is structured by an operational amplifier or the like, is the lowest among the respective structural elements of the source driver, and delays in the output of the amplification circuit are the main cause of impeding improvement in the operating speed of the source driver. To address this problem, the delay in the output of the amplification circuit has been greatly reduced, as shown by “output of single amplification circuit after speed increased” in FIG. 6B as an example, by technological improvements at the periphery of the amplification circuit in recent years. However, accompanying this, the delay in the output of the decoder circuit, which is positioned at the stage before the amplification circuit, has become the main cause of impeding improvement in the operating speed of the source driver, instead of the delay in output of the amplification circuit. Because the output of the amplification circuit depends on the output of the decoder circuit, the operating speed of the source driver has not been sufficiently improved relative to the extent that the delay in the output of the amplification circuit has been greatly reduced.
To address this, the technique disclosed in JP-A No. 2001-166741 varies the potential of the drain signal line (the data line) at the output side of the decoder circuit by the pre-charge circuit, and is therefore thought to be effective in improving the operating speed of the source driver. However, in the technique disclosed in JP-A No. 2001-166741, the supply of voltage to the data line continues during the time until the pre-charging period ends, regardless of whether or not the potential of the data line (the drain signal line) has reached the pre-charge potential (PC potential). Therefore, as is clear also from FIG. 11 of JP-A No. 2001-166741, there is the problem that, for the near-end pixels that are near to the source driver in particular, voltage is supplied to the data line for a relatively long time period even after the potential of the data line reaches the PC potential, and electric power is consumed wastefully. Further, in the technique of JP-A No. 2001-166741, as shown also in FIG. 11 of JP-A No. 2001-166741, the potential of the data line is temporarily raised to the PC potential that is higher than the final potential, and thereafter, is lowered to the final potential, and this temporary raising of the potential of the data line to the PC potential also is related to an increase in the electric power that is wastefully consumed.
Further, with regard to the technique disclosed in JP-A No. 2009-139538 as well, the supply of pre-charge voltage to the data line continues during the time until the pre-charging period ends, regardless of whether the potential of the data line has reached the pre-charge potential, as is clear also from FIG. 3 and FIG. 6 of JP-A No. 2009-139538. Therefore, in the same way as the technique of JP-A No. 2001-166741, there is the problem that electric power is consumed wastefully.